Packaging arrangements for monolithic integrated circuit components (e.g. memory chips) typically involve the use of a support/interconnect structure in which one or more circuit modules (e.g. leadless chip carriers) are physically mounted on and have signal/power connections with electrical conductor traces of a printed circuit board. In a cavity-up mounting configuration electrical connections between the chip and the signal highways of the printed circuit board may take the form of wire bond links between pads distributed along the edge or perimeter of the chip and connection regions of the conductor traces of the printed circuit board. In a cavity-down mounting configuration contact pads on an inverted chip are bonded directly to connection regions on the printed circuit board. This latter mounting/interconnect scheme has the advantage of reducing the amount of space required for completing electrical connections between the chip and the printed circuit board and, consequently, offers an increase in circuit packing density compared with conventional cavity-up printed circuit board mounting schemes. However, it substantially impedes replacement and/or repairability of the chip, since the inverted mounting of the chip prevents direct access to the interconnect bonding points, an aspect of the former technique that is especially desireable where the reworkability of a portion of a modular system may be mandated by manufacturing cost constraints but limited to only non-microelectronic high reliability procedures, as required for critical spaceborne systems.